The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit.
The Semi-Dynamic Flip-Flop (SDFF) is one of the high performance flip-flops based on the hybrid concept. In part due to its size, low clock-to-output delay, negative set-up time, and simple topology, it is considered to be one of the fastest flip-flops today. However, the SDFF is susceptible to a hazard condition, when both the input and output are at a high logic value.
FIG. 1 shows a schematic circuit diagram of a typical prior art SDFF. The data input is D 312, the clock signal is CLK0314, and the outputs are Q 316 and Qbar 317. The two inverters inv5318 and inv6319 are a xe2x80x9ckeeperxe2x80x9d circuit which maintains the value of output Qbar 317 and hence output Q 316. A transparency window for the SDFF is given by the propagation delay of the two inverters, inv1350 and inv2352, and the NAND gate 354. The internal node X 320 of the first stage 330 of the SDFF is set to a high logic level (H), when the clock CLK0314 is at a low logic level (L), i.e., the first stage 330 is pre-charged. When the input signal D 312 is H, node X 320 transitions from H to L in the transparency window where both CLK0314 and S 356 are H (transistors Mn1346, Mn2344, and Mn3342 are on). The second stage 332 captures the transition on node X 320 generated by the first stage 330 and produces output Q 316. In this case node X 320 sets output Q 316 to H via transistor Mp2374. If input D 312 is L, Mn2344 is off and node X 320 remains high during the transparency window. With node X 320 at H, output Q 316 is set at L during the transparency window (transistors Mn4370 and Mn5372 are on).
FIG. 2 is an example timing diagram for the SDFF schematic circuit diagram of FIG. 1 showing a glitch in the output. The timing diagram shows the clock signal CLK0410 representing the CLK0314 in FIG. 1. D414, X 416, and Q 418 show the signals for D 312, node X 320, and Q 316 in FIG. 1 respectively. From FIG. 2, after the rising edge 430 of CLK0410 and with D 414 set to L, X 416 remains at H and output Q 418, due to transistors Mn4370 and Mn5372, transitions from H to L 434. After another rising edge 440 of CLK0410 and with D 414 at H, X 416 transitions from H to L 442 due to transistors Mn1346, Mn2344, and Mn3342 turning on. Next output Q 418 transitions from L to H 444 due to transistor Mp2374. Thus the L to H transition of output Q, e.g., 444, is done using in effect an inverting intermediate node X 320, while the transition of output Q, e.g., 434, from H to L is done directly via nMOS transistors and avoids the slower pMOS transistors. The SDFF is used where the time critical output transitions are from L to H, e.g., 444, on output Q 316, and thus the node X transition, e.g., H to L 442, is important.
However, the asymmetrical transition times of the SDFF lead to a xe2x80x9cstatic-one-hazardxe2x80x9d at the output Q when both input D and output Q are H. In FIG. 2, before the rising edge 450 of the CLK0410, X 416 is set (or reset) to H by transistor Mp1340. Because the first stage 330 has a non-zero propagation delay from the time of the rising clock edge 450 to the time X 416 transitions from H to L 454, the second stage 332 uses the previous X (H). Hence during the time window between the rising edge 450 of the clock CLK0410 and the falling edge 454 of X 416, both Mn4370 and Mn5372 in FIG. 1 are on and the output Q 316 is pulled to low logic level (e.g., transition 452). After the propagation delay, i.e., the falling transition 454 of X 416, the transistor Mp2372 turns on (and Mn4370 turns off), and the output Q 316 is pulled to H (e.g., transition 456). Thus a glitch 462 is caused on the output Q 418 (and Qbar 420) and makes the use of the SDFF hazardous. In addition the glitch consumes power unnecessarily, as output Q 316 should not change, since input D 312 has not changed.
There is also a problem of power consumption in the unconditional keepers of the SDFF (back-to-back inverters, inv3360 and inv4362, and back-to-back inverters, inv5318 and inv6319, of FIG. 1). The keeper is used to hold the value of a dynamic node, e.g., node X 320 or output Q 316, that would otherwise be in high impedance and thus sensitive to leakage current effects and noise, especially in low-power applications where clock gating techniques are typically employed. The problem is that in order to change the value of the dynamic node, the keeper (two keepers, in the case of the SDFF) has to be overpowered, i.e., the output logic level of the keeper needs to be switched, which increases power consumption.
The power consumption and hazard problems associated with the SDFF, are demonstrative of the same or similar problems with hybrid-type flip-flops in general. Another example of a flip-flop having the same or similar type problems is the Hybrid Latch Flip-Flop (HLFF).
Therefore with the problems of hazard and power consumption with the conventional hybrid-type flip-flop, e.g., SDFF, there is a need for an improved flip-flop with fewer problems, such as fewer hazards or no hazards at all.
The present invention provides techniques, including a system and method, for reducing hazards in a conventional flip-flop, having a pre-charged stage coupled to an evaluation stage, by allowing a change in the pre-charged stage to settle before the evaluation stage processes the change. One embodiment has a substantially similar delay as the SDFF with fewer hazards and a significant reduction in power consumption.
Broadly, the present invention provides a method that reduces hazards in a flip-flop. In one embodiment this method includes a delayed reset of the output Q. The setting of the output Q, i.e., the second or evaluation stage, is disabled from being set to a low logic level by a delayed clock signal. This leaves time for the internal node X, i.e., output of the first or pre-charged stage, to transition from the high to the low logic level after the rising edge of the clock, without affecting the output Q. Consequently, the glitch that appears at Q in case of SDFF, when both the input D and output Q are at a high logic level, is prevented. In addition, a delayed pre-charge of the first stage is provided in order to prevent another hazard on the output Q. This hazard may occur because the second stage remains enabled until the delayed clock is pulled low. Hence, if the internal node X quickly charges before the second stage is disabled, a glitch on or false switching of output Q may occur. Thus, this embodiment provides a reduced-hazard flip-flop.
In another aspect of the present invention a method is provided for reducing hazards in a flip-flop, with the method including a pre-charged stage coupled to an evaluation stage by at least an internal node. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
Yet another aspect of the present invention provides a system for reducing hazards in a hybrid flip-flop including: a pre-charge stage for determining a pre-charge stage output depending upon a data input during a transparency window; and an evaluation stage for evaluating the pre-charge stage output to produce a data output during the transparency window, where the evaluation stage is enabled to change the data output to a low logic level only after the pre-charge stage determines the pre-charge stage output. The transparency window includes a time period when the pre-charge stage output is logically equivalent to an inverted value of the data input. Optionally, after the transparency window, the pre-charge stage output is restored to a default logic level, when the evaluation stage is next disabled.
The present invention also includes a system for reducing hazards in a hybrid flip-flop. The system includes a pre-charge stage for determining a pre-charge stage output depending upon a data input during a transparency window; and an evaluation stage for evaluating the pre-charge stage output to produce a data output during the transparency window, where the evaluation stage is enabled to change the data output after the pre-charge stage determines the pre-charge stage output.
A further aspect of the present invention provides a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node. First the method determines a first logic level for the internal node based on a data input to the pre-charged stage within a first section of a transparency window. The evaluation stage is disabled from setting a data output to a second logic level during the first section of the transparency window. Next the data output is determined during a second section of the transparency window based on the first logic level, where the second section follows the first section.
Another embodiment of the present invention provides a method for reducing power consumption in a hybrid flip-flop, including a pre-charged stage coupled to an evaluation stage by at least an internal node. First, an input of the pre-charged stage is set to a high logic level. The output of the evaluation stage also has a high logic level. Responsive to the setting of the input, the internal node is set to a low logic level within a beginning part of a transparency window. The evaluation stage is disabled from setting the output to a low logic level, during the beginning part of the transparency window. And the evaluation stage maintains the high logic level on the output during a remainder of the transparency window, using the low logic level of the internal node.
A further embodiment of the present invention provides a system for reducing hazards in a hybrid flip-flop including: a pre-charge stage for determining a pre-charge stage output depending upon a data input during a first part of a transparency window. The pre-charge stage includes a first conditional keeper for keeping the pre-charge stage output. And an evaluation stage for evaluating the pre-charge stage output to produce a data output during a second part of the transparency window, where the evaluation stage includes a second conditional keeper for keeping the data output.
These and other embodiments, features, aspects and advantages of the invention will become better understood with regard to the following description, appended claims and accompanying drawings.